This invention relates to a PLL circuit, and more particularly to a PLL circuit which can control the phase difference between an input signal and an output signal thereof and a signal processing apparatus using the same.
It is sometimes required for a PLL circuit which produces an output signal of a frequency f.sub.out which is N (a positive number such as, for example, 2,000) times the frequency f.sub.in of an input signal that it be capable of controlling the phase difference between the input and output signals thereof.
FIGS. 1A to 1C show a PLL circuit as a related art which can form a phase difference between an input signal and an output signal thereof which has some utility, and wherein FIG. 1A is a circuit diagram of the PLL circuit, FIG. 1B is a signal waveform diagram of the PLL circuit of FIG. 1A, and FIG. 1C is a diagram illustrating a principle of production of a phase difference by the PLL circuit of FIG. 1A.
Referring first to FIG. 1A, the PLL circuit is generally denoted at 10 and includes a phase comparison circuit 4 which compares the phases of an input signal (that is, a synchronizing signal Sync) to the PLL circuit 10 with an output signal C of a counter 7 which divides an output signal B (that is, a dot clock signal Dot Clock) of the PLL circuit 10 by 1/N (for example, to 1/2,000).
The PLL circuit 10 further includes a charge pump circuit 8 which in turn includes a charging down current source I.sub.down, a switch element 5 for connecting the charging down current source I.sub.down to a loop filter 2, a charging up current source I.sub.up, a switch element 6 for connecting the charging up current source I.sub.up to the loop filter 2, and a phase difference forming current source I1.
The charging down current source I.sub.down discharges a capacitor of the loop filter 2 via the switch element 5, which is controlled by an output signal D of the phase comparison circuit 4. The charging up current source Iup charges the capacitor of the loop filter 2 via the switch element 6, which is controlled by the other output signal of the phase comparison circuit 4. The phase difference forming current source I1 always charges up the loop filter 2.
The PLL circuit 10 further includes a voltage controlled oscillation circuit (VCO) 3 which is controlled by an output of the loop filter 2 to produce a pulse signal of a frequency corresponding to the voltage, that is, a clock pulse signal Dot Clock.
The frequency f.sub.out of the output signal B of the PLL circuit 10 depends upon the count value N of the counter 7 and is given by f.sub.out =N.f.sub.in. At a point T2 of time in FIG. 1B, both of the signal B (output signal of the PLL circuit 10) and the signal C (output signal of the counter 7) rise, and the time difference .tau.d between the rising edges of the signals B and C and a rising edge of the input signal A (at another point T1 of time) makes the phase difference between the input and output signals. In an ordinary PLL circuit, the phase difference .tau.d depends upon the current values of the charging up-current source I.sub.up and the charging down current source I.sub.down and periods within which the switch elements 5 and 6 which pass the currents therethrough are on. However, in the PLL circuit 10 shown in FIG. 1A, since it includes a current source which supplies the source I1 for always charging up on the charge-up side, the charging down current source I.sub.down flows so that it may cancel the phase difference forming current source I1.
Accordingly, since phase comparison is performed for each period (1/f.sub.in) of the input signal A as seen from FIG. 1C, a phase difference .tau.d of I1/(f.sub.in.I.sub.down) is produced, and a locked state is established with the phase difference .tau.d. This is the reason why the phase difference .tau.d is produced.
The PLL circuit having such a construction as described above with reference to FIGS. 1A to 1C has such problems as described below.
In particular, where the PLL circuit 10 is employed for a liquid crystal display apparatus, since the input signal frequency f.sub.in is, for example, 70 KHz and the output signal frequency f.sub.out is, for example, 140 MHz, if it is tried to set the phase difference .tau.d, for example, to 1 nS (nanosecond), then the current of the phase difference forming current source I1 must be set to a value equal to 1/14,285 the value of the current of the charging down current source I.sub.down. In other words, the current of the phase difference forming current source I1 must be set to a very low value comparing with the current of the charging down current source I.sub.down. In the example just mentioned, if I.sub.down =1 mA, then the current of the phase difference forming current source I1 must be set to I1=0.07 .mu.A.
However, it is really considerably difficult to produce such a weak current with a high degree of accuracy, and accordingly, it is difficult to finely control the phase difference .tau.d.
The PLL circuit is disadvantageous also in that, as apparently seen from the expression I1/(f.sub.in.I.sub.down), the phase difference .tau.d is fluctuated by a variation of the input signal frequency f.sub.in.